The present invention relates generally to content addressable memories (CAMs) and more particularly to CAMs having binary compare lines.
Due to the increasing importance of data networks, including the Internet, the prevalence of content addressable memories (CAMs) has continued to proliferate. CAMs, also referred to as xe2x80x9cassociative memories,xe2x80x9d can provide rapid matching functions that are often needed in certain packet processing hardware devices, such as routers and network switches, to name just two. In a typical packet processing operation, a device can receive a packet. The packet can include a xe2x80x9cheaderxe2x80x9d having various data fields that indicate how the packet should be processed. A device can use a matching function, provided by a CAM, to compare one or more header fields to xe2x80x9clook-upxe2x80x9d tables stored in the CAMs.
As just one example, a router can use a matching function to match the destination of an incoming packet with a xe2x80x9cforwardingxe2x80x9d table. The forwarding table can provide xe2x80x9cnexthopxe2x80x9d information that can allow the incoming packet to be transmitted to its final destination, or to another node on the way to its final destination.
The look-up tables in packet processing devices (which are typically stored in a CAM) are rarely static. That is, the entries within such a table may be constantly updated with different information. This may be particularly true in routers, which can update forwarding tables thousands of times a second.
A typical CAM can store the data values of a look-up table in one or more CAM cell arrays. CAM cell arrays can be configured into a number of entries, each of which can provide a match indication. In a compare (i.e., match) operation, data values stored within entries can be compared to a comparand value (also referred to as a xe2x80x9csearch keyxe2x80x9d). In a typical packet-processing device, a comparand value can include a field extracted from a data packet header. If a data value matches an applied comparand value, a corresponding entry can generate an active match indication. If a data value does not match an applied comparand value, a corresponding entry can generate an inactive match indication (signifying a xe2x80x9cmismatchxe2x80x9d) condition.
The structure of a CAM cell interface is shown in FIG. 1A, designated by the general reference character 100. Referring to FIG. 1A, a binary compare data CD and CD  are buffered by drivers 102 and 104, respectively. Compare lines, CMP and CMP , which can be coupled to a CAM cell, may be driven by drivers, 102 and 104. CMP and CMP  data can be compared to data stored in a CAM cell 106, and a match signal, MATCH, can be generated. Referring to FIG. 1B, waveforms for CD(CD ) and CMP(CMP ) are shown switching to their complementary levels.
An array of CAM cells is illustrated in FIG. 2. A compare word length can have a value 0 to y. A depth of the array, or a number of Match lines, can have a value of 0 to x. Components used in the construction of an array can be multiple placements of those components described in FIG. 1A. Names of the components in FIG. 2 follow the naming used in FIG. 1A, with the first digit xe2x80x9c1xe2x80x9d being replaced with a xe2x80x9c2,xe2x80x9d and with array designators added as a suffix. Referring to FIG. 2, an array can be comprised of complementary drivers 202-y and 204-y, with y=0 to ymax. CAM cells are labeled 206-xy, where a given column of cells can be coupled to the same buffered compare lines CMPy and CMP y and the given row of cells can be coupled to the same match line, MATCHx with x=0 to Xmax.
With the increase in CAM use in various applications has also come the demand for deeper CAMs having an increased number of table entries. Additionally, low-power systems may benefit from chips that have lower operating power. A negative side effect of simply increasing the memory array size can be slower matching speed and/or higher power requirements due to the increased capacitive loading on the CMP and CMP  lines. Still further, a low-side bus can have higher spike levels because the full capacitive loads on the low-going compare lines can be discharged to the bus. Resulting spikes on the bus can cause problems on those signals sensitive to bus noise, input signals for example. It is thus desirable to reduce the power requirements for larger arrays relative to CAMs constructed with conventional approaches.
According to disclosed embodiments, a content addressable memory (CAM) may include a scheme to equalize the paired compare lines coupled to the CAM cells.
According to disclosed embodiments, a content addressable memory (CAM) may include equalization circuitry between paired compare lines. An input signal to the equalization circuitry can enable a low-impedance path between compare lines in one state, and can also produce a high-impedance path between compare lines in another state.
According to another aspect of the embodiment, a transition detector can provide equalization circuitry with a pulsed signal responding to a data state change at an input of the detector. This pulsed signal can be used as an input to tri-stateable drivers with outputs coupled to the compare lines.
Further, according to another aspect of the embodiments, transition detector inputs may be coupled to one or more data input signals. These data input signals may also be coupled to delay elements having outputs coupled to tri-stateable drivers.
Another aspect of the embodiment may provide for a memory cell coupled to complementary lines having equalization circuitry there between. A control signal for the equalization circuitry can be coupled to a transition detector. A transition detector can output the control signal after detecting a logic state change on the data input.
An advantage of the disclosed embodiments is that a CAM can reduce power by having the compare lines charge-share prior to driving to the next data state.